Vlsi Design A Ripple Carry Adder Is Made Of Full Adder Cells Each Having 1 Unit (1)

VLSI design

A ripple carry adder is made of full adder cells each having 1 unit of combinational delay. To convert a four-bit ripple carry adder into a four stage pipeline adder proceed as following:

Consider the original adder as a one-stage pipeline with clock period of 4 time units and a latency of one clock cycle. Construct the retiming graph. Note the critical path delay is 4 units.

To model a four stage pipeline that will have a latency of four clock cycles, insert four clock delays on the edges that connect output nodes to the host.

Retime the graph such that the longest combinational path has one unit of delay. This can be done either by solving the constraint set problem or by moving the clock delays according to retiming rules.

Sketch the circuit schematic with flip-flops.

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